High-speed I/O interfaces between processors and double-data rate (DDR) SDRAM accommodate data transitions on both the rising and falling edges of the clock. Such interfaces work across a variety of process, voltage, and temperature (PVT) conditions with a tight “data-valid” window. This data-valid window can be significantly less than a half-clock period due to effects such as duty cycle distortion, timing uncertainty (jitter), setup/hold requirements, and the like.
FIG. 1 is an illustration of a conventional Calibrated Delay Circuit (CDC) 100 for use in the READ path between a processor (not shown) and a double-data rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) (also not shown). The CDC 100 uses a programmable delay array 101 that has delay elements therein. Various ones of the delay elements in the programmable delay array 101 can be enabled or disabled in order to increase or decrease (respectively) the delay of the incoming strobe (DQS_IN) with respect to the data (DQ) by a time TSD. The programmable delay array 101 produces positive and negative delayed strobes (DQS_PE and DQS_NE), which are used by latches 102, 103 to latch incoming double data rate data (DQ) to produce latched data (DQO_PE) and (DQO_NE). The value of TSD can be chosen so that edges of the delayed strobes (DQS_PE and DQS_NE) fall approximately in the center of a data valid window for a given operating frequency.
A calibration engine 104 is used to select the number of programmable delay elements in the programmable delay array 101 for a given PVT condition to produce TSD. The information indicating the selected number of delay elements is conveyed to the programmable delay array by means of a calibration code, CAL_CODE<N:0>, in this example.
FIG. 2 is an illustration of associated waveforms for the CDC 100 of FIG. 1. TSTP is a set up time for the data, and THLD is a hold time for the data. The data valid window (TVALID) is the time between the setup time and the hold time, and it represents the span of time when the data is best latched. In FIG. 2, the rising edge of the positive delayed strobe (DQS_PE) is shown falling within the data valid window, thereby allowing the data to be latched correctly as DQO_PE. Although the data valid window is not shown in adjacent data segments, it is apparent in FIG. 2 that the rising edge of the negative delayed strobe (DQS_NE) is shown falling within the data valid window as well, thereby allowing the data to be latched correctly as DQO_NE.
As mentioned above, the CDC 100 selects the number of programmable delay array elements to ensure that the delayed strobes DQS_PE and DQS_NE are centered within the data valid window for given PVT conditions. In practice, the temperature will change depending upon ambient conditions, and the processor supply voltage is intentionally scaled up or scaled down depending on the usage mode of the processor (e.g., high performance, low power, etc).
Changes in temperature and supply voltage can cause DQS_PE and DQS_NE to deviate from their centered positions within the data valid window. In fact, a significant change in supply voltage or temperature could cause DQS_PE and DQS_NE to fall outside the data valid window, thereby resulting in a memory access failure. One proposed solution is to operate the calibration engine 104 continuously so that the calibration code continuously tracks changes in supply voltage and temperature even if they are small changes. However, continuous operation of the calibration engine 104 will result in increased power consumption. Also, continuous operation of the calibration engine 104 will result in calibration code updates even in response to insignificant changes in supply voltage and temperature for which DQS_PE and DQS_NE would still remain within the data valid window. As memory access operations have to be suspended whenever the calibration code is being updated by the calibration engine 104, continuous operation of the calibration engine will add latency and reduce overall system performance.